Bibliography

[1]
J. Frenkil. A multi-level approach to low-power IC design. IEEE Spectrum magazine, pages 54-60, Feb. 1998.

[2]
ANSI/IEEE Std 754-1985. IEEE standard for binary floating-point arithmetic, 1985.

[3]
S. Oberman and M. Flynn. Design issues in division and other floating-point operations. IEEE Transactions on Computers, pages 154-161, February 1997.

[4]
J. M. Rabaey, M. Pedram, et al. Low Power Design Methodologies. Kluwer Academic Publishers, 1996.

[5]
H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, et al. Leading-zero anticipatory logic for high-speed floating point addition. IEEE Journal of Solid-State Circuits, pages 1157-1164, Aug. 1996.

[6]
H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, et al. A 286 MHz 64-b floating point multiplier with enhanced CG operation. IEEE Journal of Solid-State Circuits, pages 504-513, Apr. 1996.

[7]
N. Okhubo, M. Suzuki, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nagakome. A 4.4 ns CMOS 54 × 54 Multiplier using Pass-Transistor Multiplexer. IEEE Journal of Solid-State Circuits, pages 251-257, Mar. 1995.

[8]
J. L. Hennessy and D. A. Patterson. Computer Architecture: a Quantitative Approach. Morgan Kaufmann Publishers Inc., 2nd edition, 1995.

[9]
N. H. E. Weste and K. Eshraghian. Principles of CMOS VLSI Design. Addison-Wesley Publishing Company, 2nd edition, 1993.

[10]
M.D. Ercegovac and T. Lang. Division and Square Root: Digit-Recurrence Algorithms and Implementations. Kluwer Academic Publisher, 1994.

[11]
W. Nebel and J. Mermet editors. Low Power Design in Deep Submicron Electronics. Kluwer Academic Publishers, 1997.

[12]
J. M. Chang and M. Pedram. Energy minimization using multiple supply voltages. Proc. of International Symposium on Low Power Electronics and Design, pages 157-162, Aug. 1996.

[13]
E. Macii, M. Pedram, and F. Somenzi. High-level power modeling, estimation and optimization. Proc. of 34th Design Automation Conference, pages 504-511, June 1997.

[14]
A. P. Chandrakasan and R. W. Brodersen. Low Power Digital CMOS Design. Kluwer Academic Publishers, 1995.

[15]
B. Chen and I. Nedelchev. Power compiler: A gate-level power optimization and synthesys system. Proc. of International Conference on Computer Design (ICCD), pages 74-78, Oct. 1997.

[16]
A. P. Chandrakasan and R. W. Brodersen. Minimizing power consumption in digital CMOS circuits. Proceeding of IEEE, pages 498-523, Apr. 1995.

[17]
V. Tiwari, S. Malik, and P. Ashar. Guarded evaluation: pushing power management to logic synthesis/design. Proc. of International Symposium on Low Power Design, pages 221-226, Apr. 1995.

[18]
L. Benini, P. Siegel, and G. De Micheli. Automatic synthesis of gated clocks for power reduction in sequential circuits. IEEE Design and Test of Computers, pages 32-40, Dec. 1994.

[19]
T. Lang, E. Musoll, and J. Cortadella. Individual flip-flops with gated clocks for low-power datapaths. IEEE Transactions on Circuits and Systems, June 1997.

[20]
J. Monteiro, S. Devadas, and A. Ghosh. Retiming sequential circuits for low power. Proc. of 1993 International Conference on Computer-Aided Design (ICCAD), pages 398-402, Nov. 1993.

[21]
G. Hachtel, M. Hermida, A. Pardo, M. Poncino, and F. Somenzi. Re-encoding sequential circuits to reduce power dissipation. Proc. of 1994 International Conference on Computer-Aided Design (ICCAD), pages 70-73, Nov. 1994.

[22]
T. E. Williams and M. A. Horowitz. A zero-overhead self-timed 160-ns 54-b CMOS divider. IEEE Journal of Solid-State Circuits, pages 1651-1661, Nov. 1991.

[23]
G. Matsubara, N. Ide, H. Tago, S. Suzuki, and N. Goto. 30-ns 55-b shared radix 2 division and square root using a self-timed circuit. Proc. of 12th Symposium on Computer Arithmetic, pages 98-105, 1995.

[24]
F. Najm. A survey of power estimation techniques in VLSI circuits. IEEE Transactions on VLSI Systems, pages 446-455, Dec. 1994.

[25]
O. Coudert, R. Haddad, and K. Keutzer. What is the state of the art in commercial EDA tools for low power? Proc. of International Symposium on Low Power Electronics and Design, pages 181-187, Aug. 1996.

[26]
Synopsys Inc. Power Compiler. http://www.synopsys.com/products/power/

[27]
Sente Inc. WattWatcher/Architect. http://www.powereda.com/

[28]
Israel Koren. Computer Arithmetic Algorithms. Prentice-Hall, Inc. , 1993.

[29]
S. Oberman and M. Flynn. Division algorithms and implementations. IEEE Transactions on Computers, pages 833-854, August 1997.

[30]
G.S. Taylor. Radix-16 SRT dividers with overlapped quotient selection stages. Proc. of 7th Symposium on Computer Arithmetic, pages 64-71, 1985.

[31]
J. Fandrianto. Algorithm for high-speed shared radix-8 division and radix-8 square root. Proc. of 9th Symposium on Computer Arithmetic, pages 68-75, Sept. 1989.

[32]
M.D. Ercegovac, T. Lang, and P. Montuschi. Very-high radix division with prescaling and selection by rounding. IEEE Transactions on Computers, pages 909-918, August 1994.

[33]
A. Nannarelli. Implementation of a radix-512 divider. Master's thesis, Univ. of California, Irvine, June 1995.

[34]
A. Prabhu and G. Zyner. 167 MHz radix-8 divide and square root using overlapped radix-2 stages. Proc. of 12th Symposium on Computer Arithmetic, pages 155-162, July 1995.

[35]
K. Usami and M. Horowitz. Clustered voltage scaling technique for low-power design. Proc. of International Symposium on Low Power Design, pages 3-8, Apr. 1995.

[36]
G. De Micheli. Synthesis and optimization of digital circuits. McGraw-Hill, Inc., 1994.

[37]
Synopsys. Synopsys User's Manual. Synopsys Inc., 1992.

[38]
Compass Design Automation. User Manuals for COMPASS VLSI. Compass Design Automation, Inc., 1992.

[39]
R. Y. Rubinstein. Simulation and the Monte Carlo method. John Wiley & Sons, 1981.

[40]
C. Z. Mooney. Monte Carlo simulation. Sage Publications, 1997.

[41]
I. Miller, J. E. Freund, and R. Johnson. Probability and Statistics for Engineers. Prentice Hall, 1990.

[42]
R. Burch, F. Najm, P. Yang, and T. Trick. A Monte Carlo approach for power estimation. IEEE Transactions on VLSI Systems, pages 63-71, Mar. 1993.

[43]
Compass Design Automation. Passport - 0.6-Micron, 3-Volt, High-Performance Standard Cell Library. Compass Design Automation, Inc., 1994.

[44]
ST Microelectronics. CB45000 series standard cells - databook. ST Microelectronics, 1997.

[45]
P. Larsson and C. Nicol. Transition reduction in carry-save adder trees. Proc. of International Symposium on Low Power Electronics and Design, pages 85-88, Aug. 1996.

[46]
A. Nannarelli. Report on Error of PET vs. SPICE. Technical Report, Oct. 1997. Available at http://www.eng.uci.edu/ ~ alberto/pscripts/an_tech9710.ps.Z

[47]
A. Nannarelli. Short-circuit current modeling for CMOS standard cells energy consumption estimation. Technical Report, Feb. 1997. Available at http://www.eng.uci.edu/numlab/archive/pub/nl97p-01/

[48]
K. Anshumali. ACC: automatic cell characterization. Proc. of Euro ASIC '91, pages 204-209, May 1991.

[49]
A. Nannarelli. Short-Circuit Current Modeling for CMOS Standard Cells Power Characterization. Technical Report, Dec 1996. Available on the WWW at http://www.eng.uci.edu/ ~ alberto/pscripts/an_tech9612.ps.Z

[50]
A. Nannarelli. ACC: Automatic cell characterization. Web pages at URL http://www.eng.uci.edu/numlab/ACC/


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