Proc. of 2001 International Symposium on Low Power Electronics and Design (ISLPED '01), pages 322 -327, Huntington Beach, CA, USA, 6-7 Aug. 2001.
Abstract - This paper contributes a novel approach for reducing static code size and instruction fetch energy for cache-based core processors running embedded applications. Our implementation of the decompression unit guarantees fast and low-energy, on-the-fly instruction decompression at each cache lookup. The decompressor is placed outside the core boundaries; therefore, processor architecture does not need any modification, making the proposed compression approach suitable to IP-based designs. Viability of our solution is assessed through extensive benchmarking performed on a number of typical embedded programs.
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