RECENT PUBLICATIONS

2018

M. Franceschi, A. Nannarelli and M. Valle, "Tunable Floating-Point for Embedded Machine Learning Algorithms Implementation", Proc. of 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2018), p. 89-92. Prague, Czech Republic. 2-5 July 2018.

G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, M. Matta, M. Re, A. Nannarelli, D. Gelfusa, S. Lorenzo and S. Spano', "Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker", Proc. of 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2018), p. 17-20. Prague, Czech Republic. 2-5 July 2018.

A. Nannarelli. "Tunable Floating-Point for Energy Efficient Accelerators", Proc. of 25th IEEE Symposium on Computer Arithmetic, p. 33-40, Amherst, USA. 25-27 June 2018.

2017

A. Nannarelli. "A Multi-Format Floating-Point Multiplier for Power-Efficient Operations", Proc. of the 30th IEEE International System-on-Chip Conference (SOCC), p. 351-356. Munich, Germany. Sep. 2017.

A. Nannarelli, M. Re, G.C. Cardarilli, L. Di Nunzio, M. Spaziani Brunella, R. Fazzolari and F. Carbonari. "Robust Throughput Boosting for Low Latency Dynamic Partial Reconfiguration", Proc. of the 30th IEEE International System-on-Chip Conference (SOCC), p. 86-90. Munich, Germany. Sep. 2017.

E. Antelo, P. Montuschi and A. Nannarelli. "Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction", IEEE Transactions on Circuits and Systems I. Vol. 64, n. 2, pp. 409-418, Feb. 2017. DOI: 10.1109/TCSI.2016.2561518.

[book chap.] G.C. Cardarilli, A. Nannarelli, M. Re. "RNS Applications in Digital Signal Processing", Embedded Systems Design with Special Arithmetic and Number Systems, p. 181-215. Springer, 1st Edition., 2017. ISBN: 978-3-319-49741-9.

[book chap.] P. Montuschi, A. Nannarelli. "Digital Arithmetic: Division Algorithms", Encyclopedia of Computer Science and Technology, p. 348-363. CRC Press 2016, 2nd Edition., Feb. 2017. ISBN: 978-1-4822-0819-1.

2016

A. Lomuscio, G.C. Cardarilli, A. Nannarelli, and M. Re, "A Hardware Framework for on-Chip FPGA Acceleration", Proc. of the International Symposium on Integrated Circuits (ISIC 2016). Singapore. Dec. 2016.

A. Esposito, A. Lomuscio, G.C. Cardarilli, L. Di Nunzio, R. Fazzolari, A. Nannarelli, and M. Re, "Dynamically-Loaded Hardware Libraries (HLL) Technology for Audio Applications", Proc. of 50th Asilomar Conference on Signals, Systems, and Computers. Pacific Grove (CA), USA, Nov. 2016.

J. Taylor and A. Nannarelli, "Design and Simulation of a Quaternary Memory Cell based on a Physical Memristor", Proc. of 2016 IEEE Nordic Circuits and Systems Conference (NorCAS), Nov. 1-2, 2016, Copenhagen, Denmark.

A. Nannarelli. "Performance/Power Space Exploration for Binary64 Division Units", IEEE Transactions on Computers, Vol. 65, n. 5, pp. 1671-1677, May 2016. DOI: 10.1109/TC.2015.2448097.

2015

G.C. Cardarilli, L. Di Carlo, A. Nannarelli, F. M. Pandolfi, and M. Re, "A Framework for Dynamically-Loaded Hardware Library (HLL) in FPGA Acceleration", Proc. of IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), pp. 291-296, Abu Dhabi, UAE, Dec. 7-10, 2015.

A. T. Winther, W. Liu, A. Nannarelli, and S. Vrudhula. "Thermal Aware Floorplanning Incorporating Temperature Dependent Wire Delay Estimation", Microprocessors and Microsystems (MICPRO), vol. 39, n. 8, pp. 807-815, Nov. 2015.

A. Nannarelli. "Reliability in Warehouse-Scale Computing: Why Low Latency Matters", Proc. of MEDIAN Finale, Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, Tallinn, Estonia, Nov. 10-11, 2015.

G.C. Cardarilli, A. Nannarelli, M. Petricca, and M. Re, "Characterization of RNS multiply-add units for power efficient DSP", Proc. of 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, Colorado (USA), 2-5 Aug. 2015.

W. Liu and A. Nannarelli. "Power and Thermal Efficient Numerical Processing", Handbook on Data Centers, p. 263-286. Springer, New York (USA), 1st Edition, 2015. ISBN 978-1-4939-2091-4

2014

P. Albicocco, G. C. Cardarilli, A. Nannarelli, and M. Re, "Twenty Years of Research on RNS for DSP: Lessons Learned and Future Perspectives", Proc. of the Int.l Symposium on Integrated Circuits (ISIC 2014), Singapore, Dec. 2014.

J.K. Toft and A. Nannarelli, "Energy Efficient FPGA based Hardware Accelerators for Financial Applications", Proc. of the 32nd Norchip Conference, Tampere, Finland. Oct. 2014.

A. Nannarelli, "Decimal Engine for Energy-Efficient Multicore Processors", Proc. of the 22nd Int.l Conference on Very Large Scale Integration (VLSI-SoC), Playa del Carmen, Mexico, Oct. 2014.

[other]  A. Nannarelli, P. Seidel and P.T.P. Tang, "Guest Editors' Introduction: Special Section on Computer Arithmetic", IEEE Transactions on Computers, vol. 63, no. 8, pp. 1852-1853, Aug. 2014.

COMPLETE LIST OF PUBLICATIONS


Modified by Alberto Nannarelli on Friday August 31, 2018 at 16:39