Binary Floating-Point Units
This area of research is related to hardware algorithms for numerical computations and their effective implementation in terms of speed of execution, area, and energy.
A relevant part of the work is about algorithms suitable
for the hardware implementation of high-performance double-precision division and square root units. In particular, the digit-recurrence algorithm, which gives the best tradeoffs between delay and area.
Other work related to floating-point units has been also done to showcase low power or energy efficient designs, and architectural optimization.
Recent work in the area
Division and Square Root
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A. Nannarelli.
"Performance/Power Space Exploration for Binary64 Division Units",
IEEE Transactions on Computers,
DOI: 10.1109/TC.2015.2448097, Vol. 65, n. 5,
pp. 1671-1677, May 2016.
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W. Liu and A. Nannarelli.
"Power Efficient Division and Square Root Unit",
IEEE Transactions on Computers, vol. 61, no. 8, pp. 1059-1070,
Aug. 2012.
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A. Nannarelli.
"Radix-16 Combined Division and Square Root Unit",
Proc. of 20th IEEE Symposium on Computer Arithmetic,
p. 169-176,
Tubingen, Germany. 25-27 July 2011.
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Other Units
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E. Antelo, P. Montuschi and A. Nannarelli.
"Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction",
IEEE Transactions on Circuits and Systems I.
Accepted, April 2016.
Modified by Alberto Nannarelli on
Sunday October 01, 2023 at 16:48