The focus is on applying variable precision formats to ML algorithms. These formats allow to set different precisions for different operations and to tune the precision of given layers of the neural network to obtain higher power efficiency.
The idea consists in having ambient noise monitors, equipped with acoustic smart sensors, to measure the noise level and generate detailed and dynamically updated ambient noise maps in real time.
The goal is to record, process and classify the ambient noise by using algorithms typical of machine learning, and to identify hardware architectures to accelerate parts of the algorithms.
In collaboration with
This project is focused on evaluating how to obtain an efficient hardware implementation for the inference of a Neural Network (NN) exploiting different precisions and data formats for future hearing aids. In Hearing Instruments applications, the inference plays the most relevant role since training a NN does not happen on a device.
The first stage of this project is to implement NNs in software by using different precisions and to study the accuracy of a NN for the given application.
Secondly, the goal is to go from a software implementation to an efficient hardware implementation. As starting point, hardware architectures will be modeled with different data format to perform the most computationally expensive operations in the NNs. Afterwards, the goal should be the implementation of the approximated NN on an ARM processor including the overall assessment of energy-efficiency, performance, complexity and accuracy.
Platforms: FPGAs or ASICs.
In this context, Application Specific Processors (ASPs) are used to accelerate software applications in portable systems and at the Edge. FPGA-based accelerators can be designed and fine tuned to match exactly the algorithm, and FPGAs can be reconfigured at run-time by making the system adaptable to the specific workload.
Dynamic partial reconfiguration allows to re-program the hardware circuits implemented on the FPGA at run time. To have this on-the-fly reconfiguration, the main processor needs to run a run-time manager, called Hypervisor, to interface to the operating system and to the hardware drivers.
The scope of the project is to implement parts of this Hypervisor for an ARM processor.
Acceleration oriented mostly towards small computing and IoT.
Examples: Malware detection, classification algorithms, image and audio processing.
Data Centers are connected using High-speed optical communication and
powerful error correction codes are used for reliable transmission
bringing bit-error rates below 10-15. For power efficient implementation
ASIC are used. The project shall investigate FEC for Data Center
Interconnects (DCI) at targets speed at 1 Tbit/s, and beyond.
In the project, initially one of the FEC components shall be chosen and evaluated at the data rates of 400Gbit/s to 1.6Tbit/s. Then, the project can be extendet to other components.
The ASIC implementation shall be synthesized and evaluated in terms of area and power requirements.
In collaboration with Søren Forchhammer (DTU Photonics).
Advanced Verification Methodology: We are considering introduction of some more advanced digital verification methodology into our department such as System Verilog and UVM. We have already prepared a little in this direction but we would like to work more with scaffolding, generic models, checkers etc.
Cycle-wise Accurate Power Profiler: We would like to build a model for our DSP with the understanding of the power cost per instruction. The idea is to characterise the processor either in simulation or by measurement to get a library of power numbers per instruction. This could then form the basis for a code analyser that can take a program and generate a summary of the power that is consumed.
Studying techniques to reduce the power dissipation, without penalizing the performance, to prevent the temperature to rise in excess, and to increase the reliability. Targets: Floating-Point units and DSP processors (filters, etc.).
Tools that use simple cost functions to evaluate timing, area and power dissipation of small units.
The scope of this project is to use memristors as current sensors to monitor the operation of a photovoltaic (PV) array. The focus of this work is to use multiple levels of memristance to accurately calculate the energy harvested by the PV array, its power efficiency, and to detect malfunctioning cells.
Prerequisites: Good knowledge of circuit theory and Spice simulation.
Modified by Alberto Nannarelli on
Friday December 06, 2019 at 16:59
Modified by Alberto Nannarelli on Friday December 06, 2019 at 16:59