Project Description
The starting point of the project is the algorithm presented in
[1] and [2] and
the specifications on the bit length for every variable.
The project flow is depicted in Fig. 1.
We implemented the divider using the VHDL language and
hierarchical design.
We used two different tools in the realization of the divider:
Synopsys
for the behavioral model and part of the structural design and
Compass
for part of the structural and physical design.
The project flow is described by the following main steps:
-
A behavioral model of the divider was developed from the algorithm.
Using the Synopsys simulator, some simulations were carried out on this model,
choosing a set of test vectors that tested the functionality
and the correctness of the results within the bounds stated in the algorithm.
-
The unit was divided into
functional blocks. This was done manually. Each block represents a different
functionality of the system. A block could be either a combinational or
a sequential circuit, and a controller was introduced in order to have the
correct sequencing in the operations.
Then part of these functional blocks were expanded into sub-blocks
containing logic gates, adders, latches and multiplexers.
To verify these sub-blocks the same set of vectors and simulator was used.
-
Using the VHDL format, the divider rtl-model was imported into the
Compass environment for the physical design and the layout generation.
The original test vectors were converted into new patterns suitable
to the Compass mixed-mode simulator.
-
Using the Compass ASIC Synthesizer, the schematics for each block were
generated.
The Synthesizer created the gate-level model based on the synthesis
constraints (minimal area or minimal delay) and on the specified
standard cell library.
Not all the blocks were synthesised, some of them were manually designed
using the Compass schematic editor (Compass Logic Assistant).
-
QTV was run to determine the critical path.
Simulations were then carried out to see if the functionality of the
circuit had been maintained.
-
The layout was generated in a totally automatic way and then following the
netlist extraction, the extracted circuit was again simulated in order to
verify the functionality and the minimum clock cycle applicable.