The objective of this work is to develop reasonably accurate methods to evaluate the speed and area of arithmetic modules, mainly to compare these to different schemes. Such methods will be of use to the research community to guide its efforts towards schemes that have the potential for successful implementation.

In order to evaluate these methods, we consider a relatively complex arithmetic module, a radix-512 division unit. Previous evaluations of this unit have been done in terms of area and delay using two measures: full-adder units and nand2 units. In this project we implement a complete design of the radix-512 divider and compare its area and delay to the results obtained in the above mentioned evaluations.

Furthermore, we compare the implementation of the radix-512 divider in two different standard cells libraries, 1.2 um and 0.6 um, and we discuss the impact of sub-micron technologies in the design of these units.

Finally, we compare this radix-512 unit to a simpler one, a radix-4 unit, to see if the use of higher radixes can be effective in the realization of fast arithmetic units.

When the radix-512 divider was implemented, its performance showed that the speed-up over the radix-4 divider is more than double, and that it can be very effective if the priority is to have a fast circuit and the area is of lesser importance.

Project Description

Radix-512 Divider - layout 1.2 um library

Radix-512 Divider - layout 0.6 um library

VHDL Code

Results (HTML3.0 SPEC)

PDF copy (735 Kbytes)

Postscript copy (624 Kbytes)

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Alberto Nannarelli ( alberto@ece.uci.edu )