Technical Report. February 1998
Extended version of paper presented in ISLPED 98 - International Symposium on Low Power Electronics and Design, Monterey, CA
Abstract - It is known that the use of higher radices in division, reduces the number of iterations to complete the operation, but increases the complexity of the circuit. In this paper we explore the influence of the radix on the power dissipation of a floating-point divider and the power-delay tradeoffs. We compare the performance and the energy consumption per operation for a radix-4 and a radix-8 divider, realized in CMOS technology. Also we present a low-power implementation for the two dividers and some new techniques to reduce the power dissipation specific for the division algorithm. A reduction of about 40% in the energy consumption is obtained for both radices (about 70% if low-voltage gates, for dual voltage implementation, are available). Also the results show that the radix-8 divider is about 20% faster and the energy dissipated to perform a division is about the same, with respect to the radix-4.
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