1.1 CMOS inverter loaded with CL.
2.1 Block diagram of radix-r division.
2.2 Convert and round unit.
2.3 Selection function with overlapped stages.
2.4 Block diagram of radix-512 divider.
2.5 Combined division/square root unit.
3.1 Implementation of radix-4 divider.
3.2 Critical path for radix-4 implementation in Figure 3.1 .
3.3 Retiming of recurrence.
3.4 Change in the critical path. Before a) and after b) retiming
3.5 Removing buffers from MSBs. a) before, b) after.
3.6 Skewing of the select signal.
3.7 Replacing CSAs with radix-r CSAs.
3.8 b MSBs assimilated in selection function.
3.9 Low-drive cells in the recurrence.
3.10 Low-voltage cells in the recurrence.
3.11 Equalizing paths in CSA.
3.12 Partitioned selection function.
3.13 Glitch suppression using multiplexers.
3.14 Registers C and Q in the new converter.
3.15 Use of register T.
3.16 Gated flip-flop enabling function.
3.17 Two consecutive bits in the ring counter.
3.18 Clock enabling function and loading in register Q.
3.19 Gated tree. a) before, b) 50% reduction, c) 25% reduction.
3.20 Disabling SZD during recurrence iterations.
4.1 Design flow and tools.
4.2 Delay (normalized) with different VDD.
4.3 Critical path in ns.
4.4 Retiming of recurrence.
4.5 Radix-4 implementation in the carry-save adder.
4.6 Block diagram of l-p unit.
4.7 Convert-and-round unit for radix-4 divider.
4.8 Critical path for implementations with Passport/COMPASS and CB45000/Synopsys.
4.9 Percentage of energy dissipation in radix-4 divider.
4.10 Implementation of the radix-8 divider.
4.11 Retiming and critical path. a) before retiming, b) after retiming, c) after retiming and skewing the clock.
4.12 Radix-8 carry-save adder (lower).
4.13 Partitioned selection function.
4.14 Convert-and-round unit for radix-8 divider .
4.15 Low-power implementation of the radix-8 divider.
4.16 Percentage of energy dissipation in radix-8 divider.
4.17 Selection function for radix-16.
4.18 Basic implementation radix-16.
4.19 Retiming and critical path. a) before retiming, b) after retiming, c) after retiming and skewing the clock.
4.20 Radix-16 CSA.
4.21 Low-power radix-16 divider.
4.22 Percentage of energy dissipation in radix-16 divider.
4.23 Block diagram of modified divider.
4.24 Cycles and operations.
4.25 Critical path (ns) for basic implementation.
4.26 Percentage of Energy dissipation in radix-512 divider.
4.27 Retiming of the recurrence.
4.28 Retimed recurrence with Mux-R.
4.29 Critical path (ns) after retiming.
4.30 Percentage of energy dissipation in radix-512 divider.
4.31 Radix-4 combined division/square root unit.
4.32 Retiming of the recurrence. a) before retiming. b) after retiming.
4.33 Digit forwarding.
4.34 Low-power combined division/square root unit.
4.35 Percentage of energy dissipation in radix-4 combined unit.
5.1 Reduction in Ediv. Ratio to std implementation.
5.2 Energy-per-division: summary.
5.3 Energy-per-cycle: summary.
5.4 Energy-per-cycle and scaled average power for l-p implementations.
A.1 Implementation of full-adder.
A.2 Selection function.
A.3 One bit of the multiple generator.
A.4 Dual voltage: C1 is not cut-off.
A.5 Voltage level shifter.
B.1 Structure of PET.
B.2 Structure of ACC.