2.1 Example of radix-4 conversion.
2.2 Values of p in the rounding step.
2.3 Selection function for radix-4 division.
2.4 Example of radix-4 division.
2.5 Example of radix-512 division.
3.1 Selection function for radix-4 division.
3.2 Retiming does not increase number of cycles.
3.3 Modified algorithm.
3.4 Example of radix-4 modified conversion.
3.5 Example of radix-8 recoding.
4.1 Energy consumption per division for radix-4.
4.2 Radix-8: summary selection function.
4.3 Selection function for radix-8 and a = 7.
4.4 Energy-per-division for radix-8.
4.5 Area comparison.
4.6 Critical path through qL and qH.
4.7 Bit arrangement in two-level adders.
4.8 Paths in MSBs and LSBs in the recurrence.
4.9 Energy-per-division for radix-16.
4.10 Operations and signal values in retimed unit.
4.11 Energy-per-division for radix-512.
4.12 DSMUX operations.
4.13 Bits of A used in SEL.
4.14 Selection function for radix-4 combined division/square root.
4.15 Generation of F[j].
4.16 Generation of F[j] with rearranged bit-string.
4.17 Bits of A used in SEL (retimed).
4.18 Paths for MSBs and LSBs in retimed recurrence.
4.19 Summary of reductions for division and square root operations.
4.20 Comparison radix-4 divider/combined unit.
4.21 The 10 random vectors.
4.22 Percentage error in energy estimation.
5.1 Costs and benefits in the application of reduction techniques.
5.2 Energy-per-division, area, execution time and speed-up.
A.1 Result digit encoding.
A.2 Carry-look-ahead tree for 64-bit SZD.
A.3 Delay and energy comparison between level shifter and inverter.