2023

G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, R. La Cesa, A. Nannarelli, M. Re. "Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers," to appear in Proc. of the 57th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, Oct.-Nov. 2023.

G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, D. Giardino, M. Re, A. Nannarelli, and S. Spanò, "An RNS-Based Initial Absolute Position Estimator for Electrical Encoders," in IEEE Access, vol. 11, pp. 98586-98595, 2023, doi: 10.1109/ACCESS.2023.3312619.

D. Harris, J. Stine, M. Ercegovac, A. Nannarelli, K. Parry and C. Turek, "Unified Digit Selection for Radix-4 Recurrence Division and Square Root," in IEEE Transactions on Computers, doi: 10.1109/TC.2023.3305760.

2022

G.C. Cardarilli, L. Di Nunzio, R. Fazzolari, A. Nannarelli, M. Petricca, and M. Re, "Design Space Exploration based Methodology for Residue Number System Digital Filters Implementation", IEEE Transactions on Emerging Topics in Computing, vol. 10, no. 1, pp. 186-198, 1 Jan.-March 2022, doi: 10.1109/TETC.2020.2997067.

2021

D. Giardino, G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, A. Nannarelli, M. Re, and S. Spanò, "M-PSK Demodulator With Joint Carrier and Timing Recovery," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 6, pp. 1912-1916, June 2021, doi: 10.1109/TCSII.2020.3041342.

2020

A. Nannarelli. "Variable Precision 16-bit Floating-Point Vector Unit for Embedded Processors", Proc. of 27th IEEE Symposium on Computer Arithmetic, p. 96-102. Portland, USA. 7-10 June 2020. doi: 10.1109/ARITH48897.2020.00022.

G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, A. Nannarelli, M. Re and S. Spanò, "N-Dimensional Approximation of Euclidean Distance," in IEEE Transactions on Circuits and Systems II: Express Briefs. vol. 67, no. 3, pp. 565-569, Mar. 2020. doi: 10.1109/TCSII.2019.2919545.

G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, D. Giardino, M. Matta, A. Nannarelli, M. Re and S. Spanò, "FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems," Proc. of 54th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 2020, pp. 116-120, doi: 10.1109/IEEECONF51394.2020.9443368.

2019

L. Calicchia, V. Ciotoli, G.C. Cardarilli, L. Di Nunzio, R. Fazzolari, A. Nannarelli, and M. Re, "Digital Signal Processing Accelerator for RISC-V", Proc. of 26th IEEE International Conference on Electronics Circuits and Systems (ICECS 2019), p. 703-706. Genova, Italy, Nov. 2019.

G.C. Cardarilli, L. Di Nunzio, R. Fazzolari, A. Nannarelli, and M. Re, "Approximated Canonical Signed Digit for Error Resilient Intelligent Computation", Proc. of 53rd Asilomar Conference on Signals, Systems, and Computers, p. 1616-1620. Pacific Grove (CA), USA, Nov. 2019.

A. Nannarelli, "Tunable Floating-Point Adder," IEEE Transactions on Computers, vol. 68, no. 10, pp. 1553-1560, Oct. 2019.

Sergio Spanò, G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, D. Giardino, M. Matta, A. Nannarelli, and M. Re. "An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm," IEEE Access vol. 7, pp. 186340-186351, 2019.

A. Nannarelli. "Fused Multiply-Add for Variable Precision Floating-Point", Proc. of the 32nd IEEE International System-on-Chip Conference (SOCC), p. 342-347. Singapore. Sep. 2019.

M. Matta, G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, D. Giardino, A. Nannarelli, M. Re and S. Spanò, "A Reinforcement Learning Based QAM/PSK Symbol Synchronizer," in IEEE Access, vol. 7, pp. 124147-124157, 2019.

2018

M. Franceschi, A. Nannarelli and M. Valle, "Tunable Floating-Point for Artificial Neural Networks" Proc. of 25th IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), Bordeaux, France, 9-12 December 2018.

G.C. Cardarilli, L. Di Nunzio, R. Fazzolari, A. Nannarelli, and M. Re, "A Power Efficient Digital Front-End for Cognitive Radio Systems", Proc. of 52nd Asilomar Conference on Signals, Systems, and Computers. Pacific Grove (CA), USA, Oct. 2018.

M. Franceschi, A. Nannarelli and M. Valle, "Tunable Floating-Point for Embedded Machine Learning Algorithms Implementation", Proc. of 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2018), p. 89-92. Prague, Czech Republic. 2-5 July 2018.

G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, M. Matta, M. Re, A. Nannarelli, D. Gelfusa, S. Lorenzo and S. Spanò, "Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker", Proc. of 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2018), p. 17-20. Prague, Czech Republic. 2-5 July 2018.

A. Nannarelli. "Tunable Floating-Point for Energy Efficient Accelerators", Proc. of 25th IEEE Symposium on Computer Arithmetic, p. 33-40, Amherst, USA. 25-27 June 2018.

2017

A. Nannarelli. "A Multi-Format Floating-Point Multiplier for Power-Efficient Operations", Proc. of the 30th IEEE International System-on-Chip Conference (SOCC), p. 351-356. Munich, Germany. Sep. 2017.

A. Nannarelli, M. Re, G.C. Cardarilli, L. Di Nunzio, M. Spaziani Brunella, R. Fazzolari and F. Carbonari. "Robust Throughput Boosting for Low Latency Dynamic Partial Reconfiguration", Proc. of the 30th IEEE International System-on-Chip Conference (SOCC), p. 86-90. Munich, Germany. Sep. 2017.

E. Antelo, P. Montuschi and A. Nannarelli. "Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction", IEEE Transactions on Circuits and Systems I. Vol. 64, n. 2, pp. 409-418, Feb. 2017. DOI: 10.1109/TCSI.2016.2561518.

[book chap.] G.C. Cardarilli, A. Nannarelli, M. Re. "RNS Applications in Digital Signal Processing", Embedded Systems Design with Special Arithmetic and Number Systems, p. 181-215. Springer, 1st Edition., 2017. ISBN: 978-3-319-49741-9.

[book chap.] P. Montuschi, A. Nannarelli. "Digital Arithmetic: Division Algorithms", Encyclopedia of Computer Science and Technology, p. 348-363. CRC Press 2016, 2nd Edition., Feb. 2017. ISBN: 978-1-4822-0819-1.

2016

A. Esposito, A. Lomuscio, G.C. Cardarilli, L. Di Nunzio, R. Fazzolari, A. Nannarelli, and M. Re, "Dynamically-Loaded Hardware Libraries (HLL) Technology for Audio Applications", Proc. of 50th Asilomar Conference on Signals, Systems, and Computers. Pacific Grove (CA), USA, Nov. 2016.

J. Taylor and A. Nannarelli, "Design and Simulation of a Quaternary Memory Cell based on a Physical Memristor", Proc. of 2016 IEEE Nordic Circuits and Systems Conference (NorCAS), Nov. 1-2, 2016, Copenhagen, Denmark.

A. Nannarelli. "Performance/Power Space Exploration for Binary64 Division Units", IEEE Transactions on Computers, Vol. 65, n. 5, pp. 1671-1677, May 2016. DOI: 10.1109/TC.2015.2448097.

2015

G.C. Cardarilli, L. Di Carlo, A. Nannarelli, F. M. Pandolfi, and M. Re, "A Framework for Dynamically-Loaded Hardware Library (HLL) in FPGA Acceleration", Proc. of IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), pp. 291-296, Abu Dhabi, UAE, Dec. 7-10, 2015.

A. T. Winther, W. Liu, A. Nannarelli, and S. Vrudhula. "Thermal Aware Floorplanning Incorporating Temperature Dependent Wire Delay Estimation", Microprocessors and Microsystems (MICPRO), vol. 39, n. 8, pp. 807-815, Nov. 2015.

A. Nannarelli. "Reliability in Warehouse-Scale Computing: Why Low Latency Matters", Proc. of MEDIAN Finale, Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, Tallinn, Estonia, Nov. 10-11, 2015.

G.C. Cardarilli, A. Nannarelli, M. Petricca, and M. Re, "Characterization of RNS multiply-add units for power efficient DSP", Proc. of 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, Colorado (USA), 2-5 Aug. 2015.

W. Liu and A. Nannarelli. "Power and Thermal Efficient Numerical Processing", Handbook on Data Centers, p. 263-286. Springer, New York (USA), 1st Edition, 2015. ISBN 978-1-4939-2091-4

2014

P. Albicocco, G. C. Cardarilli, A. Nannarelli, and M. Re, "Twenty Years of Research on RNS for DSP: Lessons Learned and Future Perspectives", Proc. of the Int.l Symposium on Integrated Circuits (ISIC 2014), Singapore, Dec. 2014.

J.K. Toft and A. Nannarelli, "Energy Efficient FPGA based Hardware Accelerators for Financial Applications", Proc. of the 32nd Norchip Conference, Tampere, Finland. Oct. 2014.

A. Nannarelli, "Decimal Engine for Energy-Efficient Multicore Processors", Proc. of the 22nd Int.l Conference on Very Large Scale Integration (VLSI-SoC), Playa del Carmen, Mexico, Oct. 2014.

[other]  A. Nannarelli, P. Seidel and P.T.P. Tang, "Guest Editors' Introduction: Special Section on Computer Arithmetic", IEEE Transactions on Computers, vol. 63, no. 8, pp. 1852-1853, Aug. 2014.

2013

P. Albicocco, G. C. Cardarilli, A. Nannarelli, M. Petricca, and M. Re, "Truncated Multipliers through Power-Gating for Degrading Precision Arithmetic", Proc. of 47th Asilomar Conference on Signals, Systems, and Computers. pp. 2172-2176, Nov. 2013.

2012

T. Lang and A. Nannarelli, "Comments on 'Improving the Speed of Decimal Division'", IET Computers and Digital Techniques, vol. 6, no. 6, pp. 370-371, 2012.

A. Calimera, W. Liu, E. Macii, A. Nannarelli, and M. Poncino, "Power and Aging Characterization of Digital FIR Filters Architectures", in Proc. of the First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12), Annecy, France. June 2012.

P. Albicocco, G. C. Cardarilli, A. Nannarelli, M. Petricca, and M. Re, "Imprecise Arithmetic for Low Power Image Processing", in Proc. of 46th Asilomar Conference on Signals, Systems, and Computers. pp. 983-987, Nov. 2012.

M. Petricca, P. Albicocco, G. C. Cardarilli, A. Nannarelli, and M. Re, "Power Efficient Design of Parallel/Serial FIR Filters in RNS", in Proc. of 46th Asilomar Conference on Signals, Systems, and Computers. pp. 1015-1019, Nov. 2012.

J. S. Hegner, J. Sindholt, and A. Nannarelli, "Design of Power Efficient FPGA based Hardware Accelerators for Financial Applications", in Proc. of the 30th Norchip Conference, Copenhagen, Denmark. Nov. 2012.

2011

A. Nannarelli. "FPGA Based Acceleration of Decimal Operations", Proc. of International Conference on ReConFigurable Computing and FPGA's , p. 146-151, Cancun, Mexico. 30 Nov.-2 Dec. 2011.

A. T. Winther, W. Liu, A. Nannarelli and S. Vrudhula. "Temperature Dependent Wire Delay Estimation in Floorplanning", Proc. of 2011 Norchip Conference, Lund, Sweden. 14-15 Nov. 2011.

N. Borup, J. Dindrop and A. Nannarelli. "FPGA Implementation of Decimal Processors for Hardware Acceleration", Proc. of 2011 Norchip Conference, Lund, Sweden. 14-15 Nov. 2011.

P. Albicocco, G.C. Cardarilli, A. Nannarelli, M. Petricca and M. Re. "Degrading precision arithmetics for low-power FIR implementation", Proc. of 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, South Korea. 7-10 Aug. 2011.

2010

W. Liu and A. Nannarelli. "Power Dissipation Challenges in Multicore Floating-Point Units", 21st IEEE International Conference on Application-specific Sy stems, Architectures and Processors (ASAP 2010), p. 257-264. Rennes, France. July 2010.

W. Liu and A. Nannarelli. "Temperature Aware Power Optimization for Multicore Floating-Point Units", Proc. of 44th Asilomar Conference on Signals, Systems, and Computers, p. 1134-1138. Pacific Grove (CA), USA. Nov. 2010.

G.C. Cardarilli, A. Nannarelli, Y. Oster, M. Petricca, M. Re. "Design of Large Polyphase Filters in the Quadratic Residue Number System", Proc. of 44th Asilomar Conference on Signals, Systems, and Computers, p. 410-413. Pacific Grove (CA), USA. Nov. 2010.

M. Petricca, G.C. Cardarilli, A. Nannarelli, M. Re, P. Albicocco. "Degrading Precision Arithmetic for Low Power Signal Processing", Proc. of 44th Asilomar Conference on Signals, Systems, and Computers, p. 1163-1167. Pacific Grove (CA), USA. Nov. 2010.

[book chap.] G.C. Cardarilli, A. Nannarelli, M. Re. "On the Comparison of Different Number Systems in the Implementatio n of Complex FIR Filters", VLSI-SoC: Design Methodologies for SoC and SiP, p. 174-190. Springer, 1st Edition., 2010. ISBN: 978-3-642-12266-8

[book chap.] A. Nannarelli. "Low Power Hardware Platforms", Towards Green ICT, p. 131-143. River Publishers, Aalborg, Denmark. 2010. ISBN 978-87-92329-34-9.

2009

W. Liu, A. Calimera, A. Nannarelli, E. Macii, M. Poncino. "On-chip Thermal Modeling Based on SPICE Simulation", 19th International Workshop on Power And Timing Modeling, Optimization and Simulation PATMOS 2009, p. 66-75. Delft, Netherlands. Sept. 2009.

[invited] S. Gonzalez-Navarro, A. Nannarelli, C. Tsen, M. J. Schulte "Combined Decimal and Binary Floating-point Divider", Proc. of 43rd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove (CA), USA. Nov. 2009.

M. Petricca, H. Li, S. Forchhammer, A. Nannarelli, M. Re, J. D. Andersen, G.C. Cardarilli. "Hardware Implementation of Real-Time MPEG Analysis and Deblocking for Video Enhancement", Proc. of 43rd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove (CA), USA. Nov. 2009.

I. Shuli, M. Petricca, G.C. Cardarilli, A. Nannarelli, M. Re. "Multiple Constant Multiplication through Residue Number System", Proc. of 43rd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove (CA), USA. Nov. 2009.

[invited] A. Nannarelli. "Low Power Hardware Platforms", 12th International Symposium on Wireless Personal Multimedia Communications (WPMC'09). Sendai, Japan. Sept. 7-10, 2009.

2008

W. Liu and A. Nannarelli. "Power Dissipation in Division", Proc. of 42nd Asilomar Conference on Signals, Systems, and Computers, p. 1790-1794. October 2008.

[invited] A. Nannarelli, M. Re, and G.C. Cardarilli, "Reducing Power Dissipation in Pipelined Accumulators", Proc. of 42nd Asilomar Conference on Signals, Systems, and Computers, p. 2098-2101. October 2008.

G.C. Cardarilli, A. Nannarelli and M. Re, "On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters", Proc. of 16th IFIP/IEEE International Conference on Very Large Scale integration (VLSI-SoC), p. 37-41.October 2008.

L. Dadda and A. Nannarelli. "A Variant of a Radix-10 Combinational Multiplier", Proc. of 2008 IEEE International Symposium on Circuits and Systems (ISCAS), p. 3370-3373. Seattle, USA. May 18-21, 2008.

G.C. Cardarilli, L. Di Nunzio, A. Nannarelli and M. Re. "ADAPTO: Full-Adder Based Reconfigurable Architecture for Bit Level Operations", Proc. of 2008 IEEE International Symposium on Circuits and Systems (ISCAS), p. 3434-3437. Seattle, USA. May 18-21, 2008.

2007

G.C. Cardarilli, A. Del Re, A. Nannarelli and M. Re. "Impact of RNS Coding Overhead on FIR Filters Performance", Proc. of 41st Asilomar Conference on Signals, Systems, and Computers, p. 1426-1429. Asilomar Hotel and Conference Grounds, Pacific Grove, CA, USA. November 4-7, 2007.

T. Lang and A. Nannarelli. "Combined Radix-10 and Radix-16 Division Unit", Proc. of 41st Asilomar Conference on Signals, Systems, and Computers, p. 967-971. Asilomar Hotel and Conference Grounds, Pacific Grove, CA, USA. November 4-7, 2007.

T. Lang, A. Nannarelli. "A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture", IEEE Transactions on Computers, vol. 56(6), pp. 727-739, June 2007.

G.L. Bernocchi, G.C. Cardarilli, A. Del Re, A. Nannarelli and M. Re. "Low-power adaptive filter based on RNS components", Proc. of 2007 IEEE International Symposium on Circuits and Systems (ISCAS), p. 3211-3214. New Orleans (USA), May 28-31, 2007

2006

A. Nannarelli, M.S. Rasmussen, and M.B. Stuart. "A 1.5 GFLOPS Reciprocal Unit for Computer Graphics", Proc. of 40th Asilomar Conference on Signals, Systems, and Computers, p. 1682-1686. Asilomar Hotel and Conference Grounds, Pacific Grove, CA, USA. October 29 - November 1, 2006.

G.L. Bernocchi, G.C. Cardarilli, A. Del Re, A. Nannarelli and M. Re. "A hybrid RNS adaptive filter for channel equalization", Proc. of 40th Asilomar Conference on Signals, Systems, and Computers, p. 1706-1710. Asilomar Hotel and Conference Grounds, Pacific Grove, CA, USA. October 29 - November 1, 2006.

2005

E. Antelo, T. Lang, P. Montuschi and A. Nannarelli. "Digit-Recurrence Dividers with Reduced Logical Depth", IEEE Transactions on Computers, Vol. 54, p. 837-851, July 2005.

E. Antelo, T. Lang, P. Montuschi and A. Nannarelli. "Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture", Proc. of 17th Symposium on Computer Arithmetic, p. 147-152, Cape Cod (USA), June 27-29, 2005.

G.C. Cardarilli, A. Del Re, A. Nannarelli and M. Re. "Programmable Power-of-two RNS Scaler and its Application to a QRNS Polyphase Filter", Proc. of 2005 IEEE International Symposium on Circuits and Systems (ISCAS), p. 1002-1005, Kobe (Japan), May 23-26 2005.

2004

A. Del Re, A. Nannarelli, and M. Re. "A tool for automatic generation of RTL-level VHDL description of RNS FIR filters", Proc. of 2004 Design, Automation and Test in Europe Conference (DATE) Vol. 48, p. 686-687, Paris (France), Feb. 16-20, 2004.

2003

A. Nannarelli, G.C. Cardarilli, and M. Re. "Power-delay tradeoffs in residue number system", Proc. of 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Vol. V, p. 413-416, 25-28 May 2003.

2002

L. Benini, A. Macii, and A. Nannarelli. "Code compression architecture for cache energy minimisation in embedded system", IEE Proceedings - Computers and Digital Techniques Vol. 149, Iss. 4, p. 157-163, July 2002.

E. Antelo, T. Lang, P. Montuschi, and A. Nannarelli. "Fast Radix-4 Retimed Division with Selection by Comparisons", Proc. of IEEE 13th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2002), p. 185-196, San Jose, California (USA), July 17-19, 2002.

G.C. Cardarilli, A. Del Re, A. Nannarelli and M. Re. "Residue Number System Reconfigurable Datapath", Proc. of 2002 IEEE International Symposium on Circuits and Systems (ISCAS), Vol. II, p. 756-759, Phoenix, Arizona (USA), May 2002.

G.C. Cardarilli, A. Del Re, A. Nannarelli and M. Re. "Power Characterization of Digital Filters Implemented on FPGA", Proc. of 2002 IEEE International Symposium on Circuits and Systems (ISCAS), Vol. V, p. 801-804, Phoenix, Arizona (USA), May 2002.

2001

A. Del Re, A. Nannarelli, and M. Re. "Fast Prototyping Techniques Applied to the Hardware Simulation of Telecommunication Systems", Proc. of 35th Asilomar Conference on Signals, Systems, and Computers, p. 1314-1317, Asilomar Hotel and Conference Grounds, Pacific Grove, California (USA), Nov. 2001.

A. Nannarelli, M. Re, A. Del Re, G.C. Cardarilli and R. Lojacono. "High Speed RNS A/D Front End", Proc. of 6th Euro Workshop on ADC Modelling and Testing, pages 19-22, Lisbon (Portugal), September 13-14, 2001.

L. Benini, A. Macii and A. Nannarelli. "Cached-Code Compression for Energy Minimization in Embedded Processors", Proc. of International Symposium on Low Power Electronics and Design, pages 322-327, Huntington Beach, California (USA), August 6-7, 2001.

A. Nannarelli, M. Re and G.C. Cardarilli. "Tradeoffs between Residue Number System and Traditional FIR Filters", Proc. of IEEE International Symposium on Circuits and Systems, Vol. II, pages 305-308, Sydney (AUS), May 6-9, 2001.

M. Re, A. Nannarelli, G.C. Cardarilli and R. Lojacono. "FPGA Implementation of RNS to Binary Signed Conversion Architecture", Proc. of IEEE International Symposium on Circuits and Systems, Vol. IV, pages 350-353, Sydney (AUS), May 6-9, 2001.

Previous Years

A. D'Amora, A. Nannarelli, M. Re and G.C. Cardarilli. "Reducing Power Dissipation in Complex Digital Filters by using the Quadratic Residue Number System", Proc. of 34th Asilomar Conference on Signals, Systems, and Computers, pages 879-883, Asilomar Hotel and Conference Grounds, Pacific Grove, CA, USA. Oct. 29 - Nov. 1, 2000.

R. Lojacono, G.C. Cardarilli, A. Nannarelli and M. Re. "Residue Arithmetic Techniques for High Performance DSP", Problems in Modern Applied Mathematics, p. 314-318, World Scientific Engineering Society Press, 2000.

G.C. Cardarilli, A. Nannarelli and M. Re. "Reducing Power Dissipation in FIR Filters using the Residue Number System", Proc. of 43rd IEEE Midwest Symposium on Circuits and Systems, Volume 1, pages 320-323, Lansing (MI), USA, Aug. 8-11, 2000.

A. Nannarelli and T. Lang. "Low-Power Radix-4 Combined Division and Square Root", Proc. of International Conference on Computer Design, pages 236-242, Austin, Texas (USA), October 1999.

A. Nannarelli and T. Lang. "Low-Power Division: Comparison among implementations of radix 4, 8 and 16". Proc. of 14th Symposium on Computer Arithmetic, pages 60-67, Adelaide (AUS), April 1999.

A. Nannarelli and T. Lang. "Low-Power Divider", IEEE Transactions on Computers, Vol. 48, pages 2-14, January 1999.

A. Nannarelli and T. Lang. "Low-Power Radix-8 Divider", Proc. of International Conference on Computer Design, pages 420-426, Austin, Texas (USA), October 1998.

A. Nannarelli and T. Lang. "Power-Delay Tradeoffs for Radix-4 and Radix-8 Dividers", Proc. of International Symposium on Low Power Electronics and Design, pages 109-111, Monterey, California (USA), August 1998.

A. Nannarelli and T. Lang. "Low-Power Radix-4 Divider". Proc. of International Symposium on Low Power Electronics and Design, pages 205-208, Monterey, California (USA), August 1996.

Other Publications

A. Nannarelli. "Power Evaluation Tool: modeling and implementation", COMPASS User's Group Conference, San Jose, CA, April 1996.

A. Nannarelli. "Implementation of a Radix-512 Divider", M.S. Thesis, University of California, Irvine, June 1995.

A. Nannarelli and T. Lang. "Implementation of Division and Square Root: Modeling and Evaluation", Final Report for MICRO Project #94-070, University of California, 1995.

A. Nannarelli and T. Lang. "Implementation of Division with Prescaling: Modeling and Evaluation", Final Report for MICRO Project #93-088, University of California, 1994.

Modified by Alberto Nannarelli on Sunday December 10, 2023 at 18:22